Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Shao Cheng Wang; Geng Cing Lin; Yi Wei Lin; Ming Chien Tsai; Yi Wei Chiu; Shyh-Jye Jou; Ching Te Chuang; Nan Chun Lien; Wei Chiang Shih; Kuen Di Lee; Jyun Kai Chu

doi:10.1109/APCCAS.2012.6418985

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Shao Cheng Wang^*, Geng Cing Lin, Yi Wei Lin, Ming Chien Tsai, Yi Wei Chiu, Shyh-Jye Jou, Ching Te Chuang, Nan Chun Lien, Wei Chiang Shih, Kuen Di Lee, Jyun Kai Chu

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ∼ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.

原文	English
主出版物標題	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
頁面	116-119
頁數	4
DOIs	https://doi.org/10.1109/APCCAS.2012.6418985
出版狀態	Published - 1 12月 2012
事件	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, 台灣持續時間: 2 12月 2012 → 5 12月 2012

出版系列

名字	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
國家/地區	台灣
城市	Kaohsiung
期間	2/12/12 → 5/12/12

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10.1109/APCCAS.2012.6418985

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Link to publication in Scopus

引用此

Wang, S. C., Lin, G. C., Lin, Y. W., Tsai, M. C., Chiu, Y. W., Jou, S.-J., Chuang, C. T., Lien, N. C., Shih, W. C., Lee, K. D., & Chu, J. K. (2012). Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. 於 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 (頁 116-119). 文章 6418985 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2012.6418985

@inproceedings{af2bc984817a4eb894d4ff9ac5440539,

title = "Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM",

abstract = "We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ∼ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.",

author = "Wang, {Shao Cheng} and Lin, {Geng Cing} and Lin, {Yi Wei} and Tsai, {Ming Chien} and Chiu, {Yi Wei} and Shyh-Jye Jou and Chuang, {Ching Te} and Lien, {Nan Chun} and Shih, {Wei Chiang} and Lee, {Kuen Di} and Chu, {Jyun Kai}",

year = "2012",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2012.6418985",

language = "English",

isbn = "9781457717291",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "116--119",

booktitle = "2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012",

note = "2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 ; Conference date: 02-12-2012 Through 05-12-2012",

}

Wang, SC, Lin, GC, Lin, YW, Tsai, MC, Chiu, YW, Jou, S-J, Chuang, CT, Lien, NC, Shih, WC, Lee, KD & Chu, JK 2012, Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. 於 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012., 6418985, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 頁 116-119, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, 台灣, 2/12/12. https://doi.org/10.1109/APCCAS.2012.6418985

TY - GEN

T1 - Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

AU - Wang, Shao Cheng

AU - Lin, Geng Cing

AU - Lin, Yi Wei

AU - Tsai, Ming Chien

AU - Chiu, Yi Wei

AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

AU - Lien, Nan Chun

AU - Shih, Wei Chiang

AU - Lee, Kuen Di

AU - Chu, Jyun Kai

PY - 2012/12/1

Y1 - 2012/12/1

N2 - We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ∼ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.

AB - We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ∼ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.

UR - http://www.scopus.com/inward/record.url?scp=84874176906&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2012.6418985

DO - 10.1109/APCCAS.2012.6418985

M3 - Conference contribution

AN - SCOPUS:84874176906

SN - 9781457717291

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 116

EP - 119

BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012

T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012

Y2 - 2 December 2012 through 5 December 2012

ER -

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

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