Design and implementation of a Packet-in buffer system for SDN switches

Shie-Yuan Wang, Chun Hao Chang, Yi Hsuan Hsieh, Chih Liang Chou

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, we designed, implemented, and evaluated the performance of a Packet-in packet buffer system in an SDN bare metal commodity switch and Open vSwitch. In our approach, only the first packet of a new flow needs to be sent to the SDN controller via a Packet-in packet and all subsequent packets can be temporarily stored in the Packet-in packet buffer system until the arrival of the flow rule. Our experimental results show that our approach effectively prevents packets of a new flow from being dropped when they pass an SDN switch, significantly reduces the switch CPU usage, greatly reduces the control plane bandwidth usage, and greatly reduces the Packet-in packet processing load imposed on the SDN controller.

原文English
主出版物標題2017 IEEE Symposium on Computers and Communications, ISCC 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面955-960
頁數6
ISBN(電子)9781538616291
DOIs
出版狀態Published - 1 9月 2017
事件2017 IEEE Symposium on Computers and Communications, ISCC 2017 - Heraklion, Greece
持續時間: 3 7月 20177 7月 2017

出版系列

名字Proceedings - IEEE Symposium on Computers and Communications
ISSN(列印)1530-1346

Conference

Conference2017 IEEE Symposium on Computers and Communications, ISCC 2017
國家/地區Greece
城市Heraklion
期間3/07/177/07/17

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