Design and exploration of vertically stacked complementary tunneling field-effect transistors

Narasimhulu Thoti, Yiming Li*

*此作品的通信作者

研究成果: Article同行評審

摘要

The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET’s device-level simulations are implemented and deliberated in strict compliance with the experimental settings. This work comprises the study of physical and DC analyses by scaling the p- to n-CTFET separation (D pn ), being a significant factor in CFET/CTFET design for its process difficulty. By utilizing the 50% benefit in footprint, the work is further extended to CTFET static random access memory implementation and characterization with hold/read noise margin analysis.

原文English
文章編號014001
期刊Applied Physics Express
17
發行號1
DOIs
出版狀態Published - 1 1月 2024

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