Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Keyphrases

• Monolithic Integration 100%
• Junction Isolation 100%
• 4H-SiC 100%
• Isolation Structure 100%
• Planar CMOS 100%
• Vertical Power MOSFET 100%
• VDMOSFET 100%
• PMOSFET 50%
• MOSFET 50%
• Si CMOS 50%
• Substrate Bias 50%
• Breakdown Voltage 50%
• Design Criteria 50%
• High Voltage Application 50%
• Proper Design 50%
• Smart Power Integrated Circuits 50%
• Buried Junction 50%

Engineering

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Iso 100%
• Monolithic Integration 100%
• Breakdown Voltage 33%
• Substrate Bias 33%
• Design Criterion 33%
• Proper Design 33%
• Power Integrated Circuits 33%

Material Science

• Metal-Oxide-Semiconductor Field-Effect Transistor 100%
• Electronic Circuit 50%