Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Bing Yue Tsui*, Te Kai Tsai, Chia Lung Hung, Yu Xin Wen

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.

原文English
主出版物標題2022 International Electron Devices Meeting, IEDM 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面931-934
頁數4
ISBN(電子)9781665489591
DOIs
出版狀態Published - 2022
事件2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States
持續時間: 3 12月 20227 12月 2022

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2022-December
ISSN(列印)0163-1918

Conference

Conference2022 International Electron Devices Meeting, IEDM 2022
國家/地區United States
城市San Francisco
期間3/12/227/12/22

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