Design and analysis of digital data recovery circuits using oversampling

Shyh-Jye Jou*, C. H. Lin, Y. H. Chen, Z. H. Li

*此作品的通信作者

    研究成果: Article同行評審

    8 引文 斯高帕斯(Scopus)

    摘要

    A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual property. Analysis of BER due to the combined effects of the key design parameters like data jitter, clock jitter and oversampling ratio in the oversampling technique are carried out. Thus different specifications of data recovery can be designed with different design parameters. A module generator that can estimate the design parameters automatically is established. Design implementation shows the proposed all-digital data recovery circuit can achieve 3.07Gbit/s (post-layout) with 0.25m 2.5V CMOS technology standard-cell design and occupies 380×390m 2 chip area.

    原文English
    頁(從 - 到)93-101
    頁數9
    期刊IET Circuits, Devices and Systems
    1
    發行號1
    DOIs
    出版狀態Published - 19 4月 2007

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