Demonstration of CMOS Integration with High-Voltage Double-Implanted MOS in 4H-SiC

Jheng Yi Jiang, Jia Ching Hung, Kang Min Lo, Chih Fang Huang, Kung Yen Lee, Bing Yue Tsui

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)


In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V.

頁(從 - 到)78-81
期刊Ieee Electron Device Letters
出版狀態Published - 1月 2021


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