Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology

Yun Yan Chung, Jia Min Shieh, Sheng Kai Su, Hung Li Chiang, Tzu Chiang Chen, Lain Jong Li, H. S.Philip Wong, Wen Bin Jian, Chao Hsin Chien*, Kuan Cheng Lu, Chao Ching Cheng, Ming Yang Li, Chao Ting Lin, Chi Feng Li, Jyun Hong Chen, Tung Yen Lai, Kai Shin Li

*此作品的通信作者

    研究成果: Article同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).

    原文English
    文章編號8889483
    頁(從 - 到)5381-5386
    頁數6
    期刊IEEE Transactions on Electron Devices
    66
    發行號12
    DOIs
    出版狀態Published - 十二月 2019

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