Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle

Jun Ren Su, Te Wen Liao, Chung-Chih Hung

研究成果: Paper同行評審

9 引文 斯高帕斯(Scopus)

摘要

This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty-cycle. In comparison with prior art, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This study presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600MHz, and an input duty cycle ranging from 30 to 70%. It achieves a programmable output duty cycle ranging from 31.25 to 68.75% in increments of 6.25%.

原文English
頁面305-308
頁數4
DOIs
出版狀態Published - 1 12月 2012
事件2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
持續時間: 12 11月 201214 11月 2012

Conference

Conference2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家/地區Japan
城市Kobe
期間12/11/1214/11/12

指紋

深入研究「Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle」主題。共同形成了獨特的指紋。

引用此