The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.