TY - GEN
T1 - Delay-difference DLL and its-application on skewed output buffer
AU - Tsao, Ya Lan
AU - Chung, Ming Chao
AU - Jou, Shyh-Jye
PY - 2002/1/1
Y1 - 2002/1/1
N2 - The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.
AB - The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.
UR - http://www.scopus.com/inward/record.url?scp=0142002231&partnerID=8YFLogxK
U2 - 10.1109/APASIC.2002.1031586
DO - 10.1109/APASIC.2002.1031586
M3 - Conference contribution
AN - SCOPUS:0142002231
T3 - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
SP - 279
EP - 282
BT - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Y2 - 6 August 2002 through 8 August 2002
ER -