Defect-aware synthesis for reconfigurable single-electron transistor arrays

Juinn-Dar Huang, Yi Hang Chen, Jia Shin Lu

研究成果: Conference contribution同行評審

摘要

As fabrication process exploits even deeper submicron technology, power consumption is becoming one of the most critical obstacles in electronic circuit and system designs nowadays. Meanwhile, the leakage power is dominating the power consumption. Various emerging nanodevices have been developed to tackle the leakage power issue in recent years. The single-electron transistor (SET) is regarded as one of the most promising devices since several works have successfully demonstrated that it can operate with only few electrons at room temperature. Therefore, the reconfigurable SET array has been proposed to continue Moore's Law due to its ultra-low power consumption. Nevertheless, most existing synthesis algorithms assume the given SET array is defect-free. Hence, mapping a correct synthesis outcome onto a faulty SET array still yields an erroneous result. In this paper, we propose a new synthesis algorithm that guarantees the correct functionality in the presence of defects. Furthermore, the proposed technique can sometimes benefit from those defects to further reduce the mapping area. In certain cases, the required area in a faulty SET array is even smaller than that in a fault-free one. Experimental results show that our new algorithm can synthesize moderately large circuits in a reasonable runtime and achieve an area reduction of 14% as compared to the prior art.

原文English
主出版物標題25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
發行者IEEE Computer Society
ISBN(電子)9781538628805
DOIs
出版狀態Published - 13 12月 2017
事件25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates
持續時間: 23 10月 201725 10月 2017

出版系列

名字IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN(列印)2324-8432
ISSN(電子)2324-8440

Conference

Conference25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
國家/地區United Arab Emirates
城市Abu Dhabi
期間23/10/1725/10/17

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