A power MOSFET having an R//o//n area product of 160 m OMEGA multiplied by mm**2 (R//o//n equals 11 m OMEGA : BVdss equals 15 V, chip area 3. 8 mm multiplied by 3. 8 mm) which is approximately one-third of the lowest value believed reported is demonstrated. A recently developed deep-trench structure has contributed to such drastic reduction of the product. The advantages of the present structure are summarized as, low channel-resistance owing to the high-density packing capability, low spreading resistance in an epi-region due to the increased area of an accumulation layer formed along the sidewalls of the grooves, and completely eliminated parasitic JFET effect.
|頁（從 - 到）||638-641|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1 12月 1986|