Decoding unit with high issue rate for x86 superscalar microprocessors

Shin Ki Cheng*, R. Ming Shiu, Jyh-Jiun Shann

*此作品的通信作者

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

In the new generation of x86 microprocessors, superscalar techniques are used to achieve higher performance by executing multiple instructions in parallel. For compatibility and higher execution parallelism, the decoding units of these microprocessors translate the x86 instructions into primitive operations. These microprocessors translate x86 instructions by the similar way of merging address generating into load/store operations. In this paper, we develop a new translating strategy of translating isolated address generation operations. Simulation results show that, in high issue rate decoding units, translating isolated address generation operations improves the performance for 20% to 25%. Besides, we find that enhancing the store buffer with the ability of snooping result buses is important for high issue rate decoding units. Furthermore, considering the tradeoff of the hardware cost and performance, we examine the decoding rules to design a decoding unit. According to the simulation results, we suggest a good decoding rule suitable for current commercial programs.

原文English
頁面488-495
頁數8
DOIs
出版狀態Published - 1 12月 1998
事件Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China
持續時間: 14 12月 199816 12月 1998

Conference

ConferenceProceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS
城市Tainan, China
期間14/12/9816/12/98

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