Decentralized BIST methodology for system level interconnects

Chau-Chin Su, Shyh-Jye Jou

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.

原文English
頁(從 - 到)255-265
頁數11
期刊Journal of Electronic Testing: Theory and Applications (JETTA)
15
發行號3
DOIs
出版狀態Published - 1 12月 1999

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