TY - GEN
T1 - Decentralized BIST for 1149.1 and 1149.5 based interconnects
AU - Su, Chau-Chin
AU - Jou, Shyh-Jye
AU - Ting, Yuan Tzu
PY - 1996/3/11
Y1 - 1996/3/11
N2 - This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length.
AB - This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length.
UR - http://www.scopus.com/inward/record.url?scp=85030128172&partnerID=8YFLogxK
U2 - 10.1109/EDTC.1996.494136
DO - 10.1109/EDTC.1996.494136
M3 - Conference contribution
AN - SCOPUS:0029736612
T3 - Proceedings of the 1996 European Conference on Design and Test, EDTC 1996
SP - 120
EP - 125
BT - Proceedings of the 1996 European Conference on Design and Test, EDTC 1996
PB - Association for Computing Machinery, Inc
T2 - 1996 European Conference on Design and Test, EDTC 1996
Y2 - 11 March 1996 through 14 March 1996
ER -