Decentralized BIST for 1149.1 and 1149.5 based interconnects

Chau-Chin Su, Shyh-Jye Jou, Yuan Tzu Ting

研究成果: Conference contribution同行評審

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length.

原文English
主出版物標題Proceedings of the 1996 European Conference on Design and Test, EDTC 1996
發行者Association for Computing Machinery, Inc
頁面120-125
頁數6
ISBN(電子)0818674237, 9780818674235
DOIs
出版狀態Published - 11 3月 1996
事件1996 European Conference on Design and Test, EDTC 1996 - Paris, France
持續時間: 11 3月 199614 3月 1996

出版系列

名字Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

Conference

Conference1996 European Conference on Design and Test, EDTC 1996
國家/地區France
城市Paris
期間11/03/9614/03/96

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