Dead via minimization by simultaneous routing and redundant via insertion

Chih Ta Lin*, Yen Hung Lin, Guan Chan Su, Yih-Lang Li

*此作品的通信作者

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

While via failure significantly contributes to yield loss during manufacturing, post-routing redundant via insertion method is the conventional means of reducing the via failure rate, but only alive vias can be protected. As existing dead vias still lower manufacturing yield, identifying a routing result with fewer dead vias can increase the redundant via insertion rate, subsequently enhancing the yield of chips. This work presents, for the first time, a redundant-via-aware routing system to retain redundant via resources in track assignment, in which redundant vias are inserted in detailed routing. The proposed via prediction scheme performs trial route using L-shaped patterns to estimate via positions. Meanwhile, the proposed redundant-via-aware detailed router gradually relaxes the limitation on the number of generated dead vias during path searching to minimize the number of dead vias. Experimental results indicate that the proposed redundant-via-aware routing system is, to our knowledge, the first routing system that can achieve 100% redundant via insertion rate with all MCNC benchmark circuits.

原文English
主出版物標題2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
頁面657-662
頁數6
DOIs
出版狀態Published - 28 4月 2010
事件2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan
持續時間: 18 1月 201021 1月 2010

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
國家/地區Taiwan
城市Taipei
期間18/01/1021/01/10

指紋

深入研究「Dead via minimization by simultaneous routing and redundant via insertion」主題。共同形成了獨特的指紋。

引用此