Data compression for EOS on-board SAR processor

C. Y. Chang; Wai-Chi  Fang; J. C. Curlander

doi:10.1109/IGARSS.1989.576477

Data compression for EOS on-board SAR processor

C. Y. Chang^*, Wai-Chi Fang, J. C. Curlander

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

摘要

A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

原文	English
頁面	1723-1728
頁數	6
DOIs	https://doi.org/10.1109/IGARSS.1989.576477
出版狀態	Published - 1 12月 1989
事件	IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5) - Vancouver, BC, Can 持續時間: 10 7月 1989 → 14 7月 1989

Conference

Conference	IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5)
城市	Vancouver, BC, Can
期間	10/07/89 → 14/07/89

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10.1109/IGARSS.1989.576477

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title = "Data compression for EOS on-board SAR processor",

abstract = "A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.",

author = "Chang, {C. Y.} and Wai-Chi Fang and Curlander, {J. C.}",

year = "1989",

month = dec,

day = "1",

doi = "10.1109/IGARSS.1989.576477",

language = "English",

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note = "IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5) ; Conference date: 10-07-1989 Through 14-07-1989",

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T1 - Data compression for EOS on-board SAR processor

AU - Chang, C. Y.

AU - Fang, Wai-Chi

AU - Curlander, J. C.

PY - 1989/12/1

Y1 - 1989/12/1

N2 - A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

AB - A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

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U2 - 10.1109/IGARSS.1989.576477

DO - 10.1109/IGARSS.1989.576477

M3 - Paper

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SP - 1723

EP - 1728

T2 - IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5)

Y2 - 10 July 1989 through 14 July 1989

ER -

Data compression for EOS on-board SAR processor

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