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Data and Hardware Efficient Design for Convolutional Neural Network
Yue Jin Lin,
Tian-Sheuan Chang
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此作品的通信作者
神經調控醫療電子系統研究中心
電子研究所
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同行評審
50
引文 斯高帕斯(Scopus)
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Keyphrases
Hardware Efficiency
100%
Convolutional Neural Network
100%
Data Bandwidth
100%
Convolutional Layer
100%
AlexNet
66%
End-to-end Convolutional Neural Network
66%
Convolutional Neural Network Accelerator
66%
High Efficiency
33%
Computational Complexity
33%
Resource Constraints
33%
Divergence
33%
Clock Frequency
33%
Hardware Design
33%
Data Reuse
33%
Gate Count
33%
Neural Network Implementation
33%
Network Layer
33%
Parameter Optimization
33%
Hardware Resources
33%
Deep Convolutional Neural Network (deep CNN)
33%
Highly Flexible
33%
Fully Connected Layer
33%
Design Resources
33%
Kernel Size
33%
Computational Data
33%
Under Design
33%
Target Network
33%
Internal Buffer
33%
Run-time Configuration
33%
Data Efficiency
33%
Computer Science
Convolutional Neural Network
100%
Convolutional Layer
60%
Computational Complexity
20%
Hardware Design
20%
Data Reuse
20%
Network Layer
20%
Clock Frequency
20%
Hardware Resource
20%
Resource Constraint
20%
Deep Convolutional Neural Networks
20%
Network Target
20%