Crosstalk-aware power optimization with multi-bit flip-flops

Chih Cheng Hsu*, Yao Tsung Chang, Po-Hung Lin

*此作品的通信作者

研究成果: Conference contribution同行評審

6 引文 斯高帕斯(Scopus)

摘要

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger bit numbers as possible to gain more clock power saving. However, an MBFF with a larger bit number may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. To address the problem, this paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different bit numbers. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization. To our best knowledge, this is also the first work in the literature that considers the crosstalk effect for the MBFF application.

原文English
主出版物標題ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
頁面431-436
頁數6
DOIs
出版狀態Published - 26 四月 2012
事件17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
持續時間: 30 一月 20122 二月 2012

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
國家/地區Australia
城市Sydney, NSW
期間30/01/122/02/12

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