We have investigated and revealed the critical role of GIDL current for efficient erase operation in 3D vertical FeFET by developing proper test structures and demonstrated a compact long-term FeFET retention model based on nucleation-limited switching, for the first time. We also proposed novel FeFET process for low voltage operation by controlling oxygen intrusion into the gate stack. This work contributes to the realization of high-density and low-power 3D vertical FeFET.
|2021 Symposium on VLSI Technology, VLSI Technology 2021
|Institute of Electrical and Electronics Engineers Inc.
|Published - 2021
|41st Symposium on VLSI Technology, VLSI Technology 2021 - Virtual, Online, Japan
持續時間: 13 6月 2021 → 19 6月 2021
|Digest of Technical Papers - Symposium on VLSI Technology
|41st Symposium on VLSI Technology, VLSI Technology 2021
|13/06/21 → 19/06/21