CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Keyphrases

• Performance-based 100%
• On chip 100%
• Communication Architecture 100%
• Synthesis Flow 100%
• Multicycle Communication 100%
• Wire Delay 66%
• System Performance 33%
• Performance Improvement 33%
• Deep Submicron 33%
• Data Transfer 33%
• Architectural Synthesis 33%
• Placer 33%
• Distributed-register Architecture 33%
• Omponent 33%
• Umber 33%
• Global Datasets 33%

Computer Science

• Communication Architecture 100%
• Criticality 100%
• Architecture Register 66%
• Systems Performance 33%
• Performance Improvement 33%
• Architectural Synthesis 33%
• Placement Information 33%