Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD Technology

Chen Wei Hsu, Ming Dou Ker

研究成果: Article同行評審

摘要

For IC products, the I/O pins of CMOS integrated circuits (ICs) must be verified by latch-up I-test with the JEDEC JESD78F.01 standard. The high-voltage (HV) circuits and the low-voltage (LV) circuits have been integrated together in a single chip by the Bipolar-CMOS-DMOS (BCD) technology. The LV circuits were often surrounded by the n-type buried layer (NBL) isolation ring from the common p-type substrate. In the mixed-voltage IC, a parasitic latch-up path exists from the 5 V-tolerant I/O to NBL isolation ring in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD technology, which will cause the IC products failed to pass the latch-up I-test. In this work, a new isolation ring with embedded Schottky-barrier diode (SBD) was proposed and verified to overcome such a latch-up issue. According to the silicon results, the proposed Schottky-embedded isolation ring can significantly increase the holding voltage of the parasitic latch-up path. The potential latch-up danger from the 5 V-tolerant I/O to NBL isolation ring can be fully solved by the proposed Schottky-embedded isolation ring. In addition, the proposed Schottky-embedded isolation ring is fully process-compatible to the 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD technology without additional mask layer adding into the process flow.

原文English
頁(從 - 到)1-4
頁數4
期刊IEEE Transactions on Electron Devices
DOIs
出版狀態Accepted/In press - 2024

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