In this study we investigate the effects of oxidation and post-oxidation annealing temperatures on the breakdown of thin (≈25 nm) SiO2 dielectrics. We report a correlation between the amount of charge injected during high-field stressing necessary for breakdown, QBD, and the rate of positive charge trapping during high-field stressing. The correlation can be explained by a breakdown model which assumes that breakdown results from an enhancement of the electric field at the injecting interface due to the trapped positive charge. For annealing temperatures greater than ≈900°C the positive charge trapping rate increases markedly and as a result QBD decreases significantly. This positive charge trapping in the gate insulator is also the cause of the well-known sensitivity of MOS devices to ionizing radiation, and has been attributed to viscous shear flow of the SiO2. In this study it was found that QBDcan be maximized by keeping the oxidation temperature below 1000°C and that the optimum annealing temperature is approximately 900°C.