TY - JOUR
T1 - Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures
AU - Chen, Sau-Gee
AU - Huang, Shen Jui
AU - Garrido, Mario
AU - Jou, Shyh-Jye
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2014/10/1
Y1 - 2014/10/1
N2 - This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
AB - This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
KW - Bit-reversal circuit
KW - MDC
KW - MDF
KW - fast Fourier transform (FFT)
KW - natural-order FFT output
UR - http://www.scopus.com/inward/record.url?scp=84907626501&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2014.2327271
DO - 10.1109/TCSI.2014.2327271
M3 - Article
AN - SCOPUS:84907626501
SN - 1549-8328
VL - 61
SP - 2869
EP - 2877
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 10
M1 - 6849501
ER -