Configuration free SoC interconnect BIST methodology

Chau-Chin Su*, Wenliang Tseng

*此作品的通信作者

研究成果: Conference article同行評審

16 引文 斯高帕斯(Scopus)

摘要

3-state drivers are modified to exhibit wired-logic properties in test mode, it does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

原文English
頁(從 - 到)1033-1038
頁數6
期刊IEEE International Test Conference (TC)
DOIs
出版狀態Published - 1 12月 2001
事件International Test Conference 2001 Proceedings - Baltimore, MD, United States
持續時間: 30 10月 20011 11月 2001

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