Configuration free SoC interconnect BIST methodology

Chau-Chin Su; Wenliang Tseng

doi:10.1109/TEST.2001.966729

Configuration free SoC interconnect BIST methodology

Chau-Chin Su^*, Wenliang Tseng

^*此作品的通信作者

電機工程學系

研究成果: Conference article › 同行評審

16 引文斯高帕斯（Scopus）

摘要

3-state drivers are modified to exhibit wired-logic properties in test mode, it does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

原文	English
頁（從 - 到）	1033-1038
頁數	6
期刊	IEEE International Test Conference (TC)
DOIs	https://doi.org/10.1109/TEST.2001.966729
出版狀態	Published - 1 12月 2001
事件	International Test Conference 2001 Proceedings - Baltimore, MD, 美國持續時間: 30 10月 2001 → 1 11月 2001

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10.1109/TEST.2001.966729

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@article{fbd05442d8a54486bad66bd91778cc3a,

title = "Configuration free SoC interconnect BIST methodology",

abstract = "3-state drivers are modified to exhibit wired-logic properties in test mode, it does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.",

keywords = "Built-in self test, Design for testability, Interconnect testing, System-on-chip",

author = "Chau-Chin Su and Wenliang Tseng",

year = "2001",

month = dec,

day = "1",

doi = "10.1109/TEST.2001.966729",

language = "English",

pages = "1033--1038",

journal = "IEEE International Test Conference (TC)",

issn = "1089-3539",

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note = "International Test Conference 2001 Proceedings ; Conference date: 30-10-2001 Through 01-11-2001",

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AU - Tseng, Wenliang

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AB - 3-state drivers are modified to exhibit wired-logic properties in test mode, it does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

KW - Built-in self test

KW - Design for testability

KW - Interconnect testing

KW - System-on-chip

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U2 - 10.1109/TEST.2001.966729

DO - 10.1109/TEST.2001.966729

M3 - Conference article

AN - SCOPUS:0035687725

SN - 1089-3539

SP - 1033

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JO - IEEE International Test Conference (TC)

JF - IEEE International Test Conference (TC)

T2 - International Test Conference 2001 Proceedings

Y2 - 30 October 2001 through 1 November 2001

ER -

Configuration free SoC interconnect BIST methodology

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