Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design

H. P. Wen*, C. Y. Lin, Y. L. Lin


研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)


We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without impairing its trade secrete and what needs to be examined by the user to gain satisfactory level of confidence are contradictory of each other. Via PLI interface functions and Internet protocol, our proposed software enables HDL simulators (Verilog) residing in both the vendor and user's sites to concurrently simulate the IP and SOC together. Only stimulus and response defined in the IP's I/O are exchanged between the sites. Therefore, the vendor need not to create a functional model (or encrypted code) for the IP while the user is assured what he/she simulates is what he will purchase. Beside simulation speed degradation due to communication overhead, the SOC design/debug process is exactly same as if the IP is in the user's hand. Our contribution will help all IP providers expose their IPs to all potential users without human intervention and IP right infringement concern.

頁(從 - 到)233-238
期刊Proceedings of the International Symposium on System Synthesis
出版狀態Published - 1 1月 2001
事件14th International Symposium on System Synthesis (ISSS'01) - Montreal, Que., Canada
持續時間: 30 9月 20013 10月 2001


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