CompressRA+: Enhanced Register Allocation for Compressed ISAs

Modern computer architectures are increasingly characterized by the contrast between complex instruction set computers (CISC) and reduced instruction set computers (RISC). While RISC architectures favor simplicity and uniformity, their use of fixed-length instructions often leads to larger program sizes. To address this issue, some RISC instruction set architectures (ISAs), such as ARM and RISC-V, support compressed instructions to reduce code size. However, current approaches primarily rely on post-compilation compression, overlooking such opportunities during compilation. In this paper, we propose CompressRA+, a register allocation algorithm explicitly designed for compressed ISAs. Unlike prior work, such as CompressRA, which often overestimates potential compressibility and results in suboptimal register assignments, CompressRA+ incorporates a precise analysis of compression feasibility directly within the register allocation phase. This integration enables more effective utilization of compressed instruction encodings, leading to more program size reductions. We evaluated CompressRA+ on Polybench and SPEC2017, targeting the RISC-V architecture. Experimental results show that CompressRA+ achieved an average program size reduction of 0.89% on Polybench (1.64% at most) and 0.3% on SPEC2017 (1.71% at most) compared to CompressRA. The results demonstrate that integrating compression awareness into register allocation can unlock additional code size reductions beyond post-compilation compression techniques.