Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Tao Cheng; Tain Shun Wu

doi:10.1109/ISCAS.1995.519892

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Tao Cheng, Tain Shun Wu

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

13 引文斯高帕斯（Scopus）

摘要

There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

原文	English
文章編號	5099908
頁（從 - 到）	833-836
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2
DOIs	https://doi.org/10.1109/ISCAS.1995.519892
出版狀態	Published - 1995
事件	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA 持續時間: 30 4月 1995 → 3 5月 1995

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10.1109/ISCAS.1995.519892

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title = "Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's",

abstract = "There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Tao Cheng and Wu, {Tain Shun}",

year = "1995",

doi = "10.1109/ISCAS.1995.519892",

language = "English",

volume = "2",

pages = "833--836",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

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note = "Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) ; Conference date: 30-04-1995 Through 03-05-1995",

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TY - JOUR

T1 - Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Cheng, Tao

AU - Wu, Tain Shun

PY - 1995

Y1 - 1995

N2 - There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

AB - There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

UR - http://www.scopus.com/inward/record.url?scp=0029204489&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1995.519892

DO - 10.1109/ISCAS.1995.519892

M3 - Conference article

AN - SCOPUS:0029204489

SN - 0271-4310

VL - 2

SP - 833

EP - 836

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 5099908

T2 - Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)

Y2 - 30 April 1995 through 3 May 1995

ER -

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

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