Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Ming-Dou Ker*, Chung-Yu Wu, Hun Hsien Chang

*此作品的通信作者

研究成果: Article同行評審

45 引文 斯高帕斯(Scopus)

摘要

There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid the unexpected ESD damages on internal circuits. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under high-temperature environment of up to 150°C is also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.

原文English
頁(從 - 到)588-598
頁數11
期刊IEEE Transactions on Electron Devices
43
發行號4
DOIs
出版狀態Published - 1 四月 1996

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