Compiler supports and optimizations for PAC VLIW DSP processors

Yung Chia Lin; Chung Lin Tang; Chung Ju Wu; Ming Yu Hung; Yi-Ping You; Ya Chiao Moo; Sheng Yuan Chen; Jenq Kuen Lee

doi:10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors

Yung Chia Lin^*, Chung Lin Tang, Chung Ju Wu, Ming Yu Hung, Yi-Ping You, Ya Chiao Moo, Sheng Yuan Chen, Jenq Kuen Lee

^*此作品的通信作者

資訊科學與工程研究所

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

原文	English
主出版物標題	Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers
頁面	466-474
頁數	9
DOIs	https://doi.org/10.1007/978-3-540-69330-7_34
出版狀態	Published - 2006
事件	18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 - Hawthorne, NY, United States 持續時間: 20 10月 2005 → 22 10月 2005

出版系列

名字	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
卷	4339 LNCS
ISSN（列印）	0302-9743
ISSN（電子）	1611-3349

Conference

Conference	18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005
國家/地區	United States
城市	Hawthorne, NY
期間	20/10/05 → 22/10/05

存取文件

10.1007/978-3-540-69330-7_34

其它文件與鏈接

Link to publication in Scopus

引用此

Lin, Y. C., Tang, C. L., Wu, C. J., Hung, M. Y., You, Y.-P., Moo, Y. C., Chen, S. Y., & Lee, J. K. (2006). Compiler supports and optimizations for PAC VLIW DSP processors. 於 Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers (頁 466-474). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 4339 LNCS). https://doi.org/10.1007/978-3-540-69330-7_34

Lin, Yung Chia ; Tang, Chung Lin ; Wu, Chung Ju 等. / Compiler supports and optimizations for PAC VLIW DSP processors. Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. 頁 466-474 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{819e17d6dea54ff99ad6b41b0e28b5ab,

title = "Compiler supports and optimizations for PAC VLIW DSP processors",

abstract = "PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.",

author = "Lin, {Yung Chia} and Tang, {Chung Lin} and Wu, {Chung Ju} and Hung, {Ming Yu} and Yi-Ping You and Moo, {Ya Chiao} and Chen, {Sheng Yuan} and Lee, {Jenq Kuen}",

year = "2006",

doi = "10.1007/978-3-540-69330-7_34",

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booktitle = "Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers",

note = "18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005 ; Conference date: 20-10-2005 Through 22-10-2005",

}

Lin, YC, Tang, CL, Wu, CJ, Hung, MY, You, Y-P, Moo, YC, Chen, SY & Lee, JK 2006, Compiler supports and optimizations for PAC VLIW DSP processors. 於 Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 卷 4339 LNCS, 頁 466-474, 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005, Hawthorne, NY, United States, 20/10/05. https://doi.org/10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors. / Lin, Yung Chia; Tang, Chung Lin; Wu, Chung Ju 等.
Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. p. 466-474 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 4339 LNCS).

研究成果: Conference contribution › 同行評審

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T1 - Compiler supports and optimizations for PAC VLIW DSP processors

AU - Lin, Yung Chia

AU - Tang, Chung Lin

AU - Wu, Chung Ju

AU - Hung, Ming Yu

AU - You, Yi-Ping

AU - Moo, Ya Chiao

AU - Chen, Sheng Yuan

AU - Lee, Jenq Kuen

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N2 - PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

AB - PAC DSP is a novel VLIW DSP processor exceedingly utilized with port-restricted, distinct partitioned register file structures in addition to the heterogeneous clustered datapath architecture to attain low power consumption and reduced die size; however, these architectural features lend new challenges to the compiler construction. This paper describes our employment of the Open Research Compiler (ORC) infrastructure on PAC DSP architectures and the specific compilation design. Preliminary results indicated that our compiler development for PAC DSP is effective for the architecture and the evaluation is useful for the refinement of the architecture. Our experiences in designing the compiler support for heterogeneous VLIW DSP processors with irregular resource constraints may benefit the similar architectures.

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T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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Lin YC, Tang CL, Wu CJ, Hung MY, You YP, Moo YC 等. Compiler supports and optimizations for PAC VLIW DSP processors. 於 Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Revised Selected Papers. 2006. p. 466-474. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-69330-7_34

Compiler supports and optimizations for PAC VLIW DSP processors

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