Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits

Hui Wen Tsai, Ming-Dou Ker

    研究成果: Conference contribution同行評審

    摘要

    A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-μm BCD process to improve latchup immunity.

    原文English
    主出版物標題2015 European Conference on Circuit Theory and Design, ECCTD 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781479998777
    DOIs
    出版狀態Published - 16 10月 2015
    事件European Conference on Circuit Theory and Design, ECCTD 2015 - Trondheim, Norway
    持續時間: 24 8月 201526 8月 2015

    出版系列

    名字2015 European Conference on Circuit Theory and Design, ECCTD 2015

    Conference

    ConferenceEuropean Conference on Circuit Theory and Design, ECCTD 2015
    國家/地區Norway
    城市Trondheim
    期間24/08/1526/08/15

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