Compact Model for Trap Assisted Tunneling based GIDL

Chetan Kumar Dabhi*, Girish Pahwa, Sayeef Salahuddin, Chenming Hu

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.

原文English
主出版物標題2022 Device Research Conference, DRC 2022
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665498838
DOIs
出版狀態Published - 2022
事件2022 Device Research Conference, DRC 2022 - Columbus, 美國
持續時間: 26 6月 202229 6月 2022

出版系列

名字Device Research Conference - Conference Digest, DRC
2022-June
ISSN(列印)1548-3770

Conference

Conference2022 Device Research Conference, DRC 2022
國家/地區美國
城市Columbus
期間26/06/2229/06/22

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