TY - GEN
T1 - Compact Model for Trap Assisted Tunneling based GIDL
AU - Dabhi, Chetan Kumar
AU - Pahwa, Girish
AU - Salahuddin, Sayeef
AU - Hu, Chenming
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.
AB - State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.
UR - http://www.scopus.com/inward/record.url?scp=85137735068&partnerID=8YFLogxK
U2 - 10.1109/DRC55272.2022.9855798
DO - 10.1109/DRC55272.2022.9855798
M3 - Conference contribution
AN - SCOPUS:85137735068
T3 - Device Research Conference - Conference Digest, DRC
BT - 2022 Device Research Conference, DRC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 Device Research Conference, DRC 2022
Y2 - 26 June 2022 through 29 June 2022
ER -