@inproceedings{49becb52b6604cd0bdc532a62aaf95a2,
title = "Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process",
abstract = "An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-μim shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.",
author = "Ming-Dou Ker and Lo, {Wen Yu} and Chen, {Tung Yang} and Howard Tang and Chen, {S. S.} and Wang, {M. C.}",
year = "2001",
month = mar,
day = "28",
doi = "10.1109/ISQED.2001.915241",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "267--272",
booktitle = "Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001",
address = "United States",
note = "2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 ; Conference date: 26-03-2001 Through 28-03-2001",
}