TY - JOUR
T1 - Compact IDCT processor for HDTV applications
AU - Chang, Tian-Sheuan
AU - Guo, Jiun-In
AU - Jen, Chein Wei
PY - 1999/12/1
Y1 - 1999/12/1
N2 - This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100 Mpixels/sec throughput.
AB - This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100 Mpixels/sec throughput.
UR - http://www.scopus.com/inward/record.url?scp=0033331359&partnerID=8YFLogxK
U2 - 10.1109/SIPS.1999.822320
DO - 10.1109/SIPS.1999.822320
M3 - Conference article
AN - SCOPUS:0033331359
SN - 1520-6130
SP - 151
EP - 158
JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
T2 - 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation'
Y2 - 20 October 1999 through 22 October 1999
ER -