Combined frame memory architecture for motion compensation in video decoding

Nelson Yen Chung Chang, Tian-Sheuan Chang

    研究成果: Conference article同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    This paper proposes a combined frame memory architecture which is smaller in size and is potential in reducing power consumption compared to the most commonly used ping-pong frame memory. The combined frame memory maps both reference frame data and current frame data onto one single frame memory instead of two in ping-pong architecture. Together with the characteristic of high percentage of MBs with zero-valued MVs and no residual, the combined frame memory architectures is evaluated to be able to reduce not only the memory size, but also the average energy consumption and memory access latency for applications like surveillance, video phone, and video conference. According to the statistics and analysis result, the proposed combined frame memory architecture memory size is only 57% compared to ping-pong architecture. The proposed combined frame memory architecture can reduce up to 83% of average latency and 39% of average power consumption compared to ping-pong frame memory architecture.

    原文English
    文章編號1464960
    頁(從 - 到)1806-1809
    頁數4
    期刊Proceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    出版狀態Published - 2005
    事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    持續時間: 23 5月 200526 5月 2005

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