Recent advances in silicon technology have enabled the possibility of constructing CMOS-based Gb/s communication systems beyond the 50 GHz frequency range with fully integrated transmitters and receivers already demonstrated at 60, 100, and 150 GHz [1–6]. These transceivers are a relatively new topic and the research emphasis remains on the circuit design aspects of implementing the major building blocks (LNAs, PAs, VCOs, etc.) at such high frequencies. While attaining circuit performance is critical for the future commercialization of these mm-wave technologies, process sensitivity and die yielding are equally critical for delivering a robust commercial product. This chapter discusses the unique effects of process variation at high mm-wave frequencies and several new calibration schemes to optimize their performance. While conventional microwave RFIC design is typically accomplished by de-sensitizing a circuit design to process parameters at the expense of peak performance, the design margins remain much lower at mm-wave. Trading off performance is no longer a suitable solution and, instead, internal calibration and feedback approaches become the only clear path to commercialization.