TY - GEN
T1 - CMOS-RRAM based In-Memory Hamming Distance Calculation Technique
AU - Kumar, Manoj
AU - Wu, Ming Hung
AU - Hou, Tuo Hung
AU - Suri, Manan
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - We designed a CMOS-RRAM based in-memory Hamming Distance (HD) calculation technique providing additional degree of mismatch as compared to Content Addressable Memories (CAMs). One 2T2R (2-Transistor, 2-RRAM) cell is considered to store a single encoded bit of ternary information, while both the RRAM cells are programmed to complementary resistance states. The net current flowing through the 2T2R unit cell results in the HD. Moreover, the HD for various possible combinations of 16-bit input and stored data was shown through array level circuit simulations with integrated Transimpedence Amplifiers (TIAs) to convert row-wise accumulated current into output voltage. The 2T2R-based technique exhibits minimum 3× area and geq 3.6× power saving as compared to existing CMOSNVM (Non-Volatile Memory) counterparts.
AB - We designed a CMOS-RRAM based in-memory Hamming Distance (HD) calculation technique providing additional degree of mismatch as compared to Content Addressable Memories (CAMs). One 2T2R (2-Transistor, 2-RRAM) cell is considered to store a single encoded bit of ternary information, while both the RRAM cells are programmed to complementary resistance states. The net current flowing through the 2T2R unit cell results in the HD. Moreover, the HD for various possible combinations of 16-bit input and stored data was shown through array level circuit simulations with integrated Transimpedence Amplifiers (TIAs) to convert row-wise accumulated current into output voltage. The 2T2R-based technique exhibits minimum 3× area and geq 3.6× power saving as compared to existing CMOSNVM (Non-Volatile Memory) counterparts.
UR - http://www.scopus.com/inward/record.url?scp=85193212303&partnerID=8YFLogxK
U2 - 10.1109/EDTM58488.2024.10511908
DO - 10.1109/EDTM58488.2024.10511908
M3 - Conference contribution
AN - SCOPUS:85193212303
T3 - IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024
BT - IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 8th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2024
Y2 - 3 March 2024 through 6 March 2024
ER -