TY - GEN
T1 - CMOS power amplifier with ESD protection design merged in matching network
AU - Shiu, Yu D.
AU - Huang, Bo Shih
AU - Ker, Ming-Dou
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-μm CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.
AB - A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-μm CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.
UR - http://www.scopus.com/inward/record.url?scp=50649097676&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2007.4511118
DO - 10.1109/ICECS.2007.4511118
M3 - Conference contribution
AN - SCOPUS:50649097676
SN - 1424413788
SN - 9781424413782
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 825
EP - 828
BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Y2 - 11 December 2007 through 14 December 2007
ER -