CMOS on-chip ESD protection design with substrate-triggering technique

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*此作品的通信作者

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

To increase the ESD robustness and to reduce the trigger voltage of the ESD protection devices, a substrate-triggering technique is proposed to effectively enhance the ESD-protection efficiency of CMOS on-chip ESD protection circuits in submicron CMOS technologies. With suitable substrate bias, the ESD protection devices can sustain much higher ESD-stress voltage within small layout area. Two practical design examples of the input ESD protection circuit and the VDD-to-VSS ESD clamp circuit are designed by using the substrate-triggering technique to verify the ESD protection efficiency.

原文English
頁面273-276
頁數4
DOIs
出版狀態Published - 1 12月 1998
事件Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal
持續時間: 7 9月 199810 9月 1998

Conference

ConferenceProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
城市Lisboa, Portugal
期間7/09/9810/09/98

指紋

深入研究「CMOS on-chip ESD protection design with substrate-triggering technique」主題。共同形成了獨特的指紋。

引用此