CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

Keyphrases

• BiCMOS Technology 33%
• CMOS Technology 33%
• Effective Rate of Protection 33%
• Electrostatic Discharge (ESD) Protection 100%
• ESD Current 33%
• ESD Damage 33%
• ESD Protection Device 100%
• High-speed Applications 33%
• Layout Area 33%
• Low Impedance 33%
• Negative Polarity 66%
• NMOS Device 33%
• On chip 100%
• On-chip ESD Protection 33%
• PMOS Device 33%
• Polysilicon Resistor 33%
• Positive Polarity 66%
• Protection Circuit 100%
• RC Delay 33%
• Shunt Path 33%
• Trigger Voltage 100%

Engineering

• Electrostatic Discharge 100%
• Experimental Result 100%
• Nodes 100%
• Polysilicon 100%
• Speed Application 100%