Clock tree aware post-global placement optimization

Hong Yan Su, Po Ting Chiang, Radhamanjari Samanta, Yih-Lang Li

研究成果: Conference contribution同行評審

摘要

Power consumption is one of the key optimization objectives for modern integrated circuit designs. More than 40% of the total power consumption is contributed by clock trees due to their high frequency of switching and high capacitance. In the traditional physical design flow, placement is done before clock tree synthesis (CTS). CTS constructs a tree to connect the clock source with all the registers. Therefore, optimization of clock trees is limited by the quality of register placement. This paper proposes a post-global placement optimization procedure that integrates a fast three stage CTS method based on modified k-means clustering technique into a global placer. The fast three stage CTS constructs a virtual clock tree to guide global placement to favor CTS. Then a multi-level clock net contractive force according to the virtual clock tree is inserted to optimize register locations for reducing the clock tree wirelength. The experimental results show that the proposed optimization approach can reduce both the clock tree wirelength and clock net switching power at the cost of slight increase in half perimeter wirelength (HPWL).

原文English
主出版物標題2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面86-90
頁數5
ISBN(電子)9781538635063
DOIs
出版狀態Published - 29 十二月 2017
事件2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017 - Nanjing, China
持續時間: 8 十一月 201711 十一月 2017

出版系列

名字2017 2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
2017-November

Conference

Conference2nd International Conference on Integrated Circuits and Microsystems, ICICM 2017
國家/地區China
城市Nanjing
期間8/11/1711/11/17

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