Clock-tree aware multibit flip-flop generation during placement for power optimization

Keyphrases

• Power Optimization 100%
• Clock Tree 100%
• Multi-bit Flip-flop 100%
• Flip-flop 50%
• Combinational Logic 33%
• Logic Cell 33%
• Tight 16%
• Power Reduction 16%
• Latency 16%
• Time Constraints 16%
• Result-oriented 16%
• Circuit Performance 16%
• Optimization Techniques 16%
• Less Power 16%
• Integrated Circuit Design 16%
• Problem Formulation 16%
• Effective Power 16%
• Latency Minimization 16%
• Nanometer Integrated Circuits 16%

Computer Science

• Power Optimization 100%
• Combinational Logic 100%
• Experimental Result 50%
• Optimization Technique 50%
• Timing Constraint 50%
• Integrated Circuit Design 50%
• Problem Formulation 50%