Clock-tree aware multibit flip-flop generation during placement for power optimization

Po-Hung Lin, Chih Cheng Hsu, Yu Chuan Chen

研究成果: Article同行評審

19 引文 斯高帕斯(Scopus)

摘要

Utilizing multibit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit design. Most of the previous works apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop (FF) merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize FF power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only FF power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees when generating MBFFs during placement.

原文English
文章編號6975058
頁(從 - 到)280-292
頁數13
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
34
發行號2
DOIs
出版狀態Published - 1 二月 2015

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