Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization

Sheng Chin Hung; Chieh Yang Chen; Chien Hsueh Chiang; Yiming Li

doi:10.3233/978-1-61499-484-8-157

Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization

Sheng Chin Hung, Chieh Yang Chen, Chien Hsueh Chiang, Yiming Li

電信工程研究所

研究成果: Conference contribution › 同行評審

摘要

In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.

原文	English
主出版物標題	Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014
編輯	William Cheng-Chung Chu, Stephen Jenn-Hwa Yang, Han-Chieh Chao
發行者	IOS Press
頁面	157-166
頁數	10
ISBN（電子）	9781614994831
DOIs	https://doi.org/10.3233/978-1-61499-484-8-157
出版狀態	Published - 12 1月 2015
事件	International Computer Symposium, ICS 2014 - Taichung, Taiwan 持續時間: 12 12月 2014 → 14 12月 2014

出版系列

名字	Frontiers in Artificial Intelligence and Applications
卷	274
ISSN（列印）	0922-6389

Conference

Conference	International Computer Symposium, ICS 2014
國家/地區	Taiwan
城市	Taichung
期間	12/12/14 → 14/12/14

存取文件

10.3233/978-1-61499-484-8-157

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Link to publication in Scopus

引用此

Hung, S. C., Chen, C. Y., Chiang, C. H., & Li, Y. (2015). Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization. 於 W. C-C. Chu, S. J-H. Yang, & H-C. Chao (編輯), Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014 (頁 157-166). (Frontiers in Artificial Intelligence and Applications; 卷 274). IOS Press. https://doi.org/10.3233/978-1-61499-484-8-157

Hung, Sheng Chin ; Chen, Chieh Yang ; Chiang, Chien Hsueh 等. / Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization. Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014. 編輯 / William Cheng-Chung Chu ; Stephen Jenn-Hwa Yang ; Han-Chieh Chao. IOS Press, 2015. 頁 157-166 (Frontiers in Artificial Intelligence and Applications).

@inproceedings{499fb511c40e4c3bb81d3ed462a58b56,

title = "Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization",

abstract = "In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.",

keywords = "a-Si:H TFTs, amorphous silicon gate driver circuits, display panel design optimization, multiobjective evolutionary algorithm, unified optimization framework",

author = "Hung, {Sheng Chin} and Chen, {Chieh Yang} and Chiang, {Chien Hsueh} and Yiming Li",

year = "2015",

month = jan,

day = "12",

doi = "10.3233/978-1-61499-484-8-157",

language = "English",

series = "Frontiers in Artificial Intelligence and Applications",

publisher = "IOS Press",

pages = "157--166",

editor = "Chu, {William Cheng-Chung} and Yang, {Stephen Jenn-Hwa} and Han-Chieh Chao",

booktitle = "Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014",

address = "Netherlands",

note = "International Computer Symposium, ICS 2014 ; Conference date: 12-12-2014 Through 14-12-2014",

}

Hung, SC, Chen, CY, Chiang, CH & Li, Y 2015, Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization. 於 WC-C Chu, SJ-H Yang & H-C Chao (編輯), Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014. Frontiers in Artificial Intelligence and Applications, 卷 274, IOS Press, 頁 157-166, International Computer Symposium, ICS 2014, Taichung, Taiwan, 12/12/14. https://doi.org/10.3233/978-1-61499-484-8-157

Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization. / Hung, Sheng Chin; Chen, Chieh Yang; Chiang, Chien Hsueh 等.
Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014. 編輯 / William Cheng-Chung Chu; Stephen Jenn-Hwa Yang; Han-Chieh Chao. IOS Press, 2015. p. 157-166 (Frontiers in Artificial Intelligence and Applications; 卷 274).

研究成果: Conference contribution › 同行評審

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AU - Hung, Sheng Chin

AU - Chen, Chieh Yang

AU - Chiang, Chien Hsueh

AU - Li, Yiming

PY - 2015/1/12

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N2 - In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.

AB - In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < -9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.

KW - a-Si:H TFTs

KW - amorphous silicon gate driver circuits

KW - display panel design optimization

KW - multiobjective evolutionary algorithm

KW - unified optimization framework

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BT - Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014

A2 - Chu, William Cheng-Chung

A2 - Yang, Stephen Jenn-Hwa

A2 - Chao, Han-Chieh

PB - IOS Press

T2 - International Computer Symposium, ICS 2014

Y2 - 12 December 2014 through 14 December 2014

ER -

Hung SC, Chen CY, Chiang CH, Li Y. Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization. 於 Chu WC-C, Yang SJ-H, Chao H-C, 編輯, Intelligent Systems and Applications - Proceedings of the International Computer Symposium, ICS 2014. IOS Press. 2015. p. 157-166. (Frontiers in Artificial Intelligence and Applications). doi: 10.3233/978-1-61499-484-8-157

Circuit-simulation-based multi-objective evolutionary algorithm with multi-level clock driving technique for a-Si:H TFTs gate driver circuit design optimization

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