Circuit performance of double-gate SOI CMOS

C. H. Lin, Pin Su, Y. Taur, X. Xi, I. He, A. M. Niknejad, M. Chan, Chen-Ming Hu

研究成果: Conference contribution同行評審

13 引文 斯高帕斯(Scopus)

摘要

As CMOS technology is fast moving toward the scaling limit, the double-gate (DG) MOSFETs is considered the most promising structure to suppress the short channel effect for a given equivalent gate oxide thickness by using two gates to control the channel [1]. There are two main types of DG MOSFETs: ( 1 ) the symmetric DG (SDG) device with both gates of identical work functions, and (2) the asymmetric'DG (ADG) device with different work functions for the gates. Although the characteristics of SDG and ADG device have been investigated by many groups (2-4), the relative circuit performance of these two devices still remains controversial. In this paper, the performance of DG MOSFETs from the circuit-design perspective is examined via simulation using device structures based on the ITRS specification [ 5 ] . The propagation delay (l,J and energy dissipation of DG CMOS inverter chains with different number of fan-out (FO) are investigated. Load capacitors are added to the output node of each inverter to simulate the parasitic wiring capacitance (C,1ml) between two stages (Fig. 1).

原文English
主出版物標題2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面266-267
頁數2
ISBN(電子)0780381394, 9780780381391
DOIs
出版狀態Published - 2003
事件International Semiconductor Device Research Symposium, ISDRS 2003 - Washington, 美國
持續時間: 10 12月 200312 12月 2003

出版系列

名字2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings

Conference

ConferenceInternational Semiconductor Device Research Symposium, ISDRS 2003
國家/地區美國
城市Washington
期間10/12/0312/12/03

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