Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCos IC product

Ming-Dou Ker; Shih Hung Chen; Tang Kui Tseng

doi:10.1109/APCCAS.2004.1413011

Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCos IC product

Ming-Dou Ker^*, Shih Hung Chen, Tang Kui Tseng

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研究成果 › 同行評審

摘要

Successful circuit design to achieve the whole-chip electrostatic discharge (ESD) protection for an UXGA/HDTV LCoS IC product with a die size of 20289.6μm × 16841.5μm has been proposed and practically verified in 0.35-μm 3.3V/12V CMOS process. This LCoS IC with both of low-voltage (LV) and high-voltage (HV) ESD protection circuits can sustain ESD stresses of 3.5kV and 200V in human-body-model (HBM) and machine-model (MM) ESD test standards, respectively.

原文	English
頁面	845-848
頁數	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1413011
出版狀態	Published - 1 12月 2004
事件	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, 台灣持續時間: 6 12月 2004 → 9 12月 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家/地區	台灣
城市	Tainan
期間	6/12/04 → 9/12/04

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10.1109/APCCAS.2004.1413011

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author = "Ming-Dou Ker and Chen, {Shih Hung} and Tseng, {Tang Kui}",

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Y1 - 2004/12/1

N2 - Successful circuit design to achieve the whole-chip electrostatic discharge (ESD) protection for an UXGA/HDTV LCoS IC product with a die size of 20289.6μm × 16841.5μm has been proposed and practically verified in 0.35-μm 3.3V/12V CMOS process. This LCoS IC with both of low-voltage (LV) and high-voltage (HV) ESD protection circuits can sustain ESD stresses of 3.5kV and 200V in human-body-model (HBM) and machine-model (MM) ESD test standards, respectively.

AB - Successful circuit design to achieve the whole-chip electrostatic discharge (ESD) protection for an UXGA/HDTV LCoS IC product with a die size of 20289.6μm × 16841.5μm has been proposed and practically verified in 0.35-μm 3.3V/12V CMOS process. This LCoS IC with both of low-voltage (LV) and high-voltage (HV) ESD protection circuits can sustain ESD stresses of 3.5kV and 200V in human-body-model (HBM) and machine-model (MM) ESD test standards, respectively.

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

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Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCos IC product

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