CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device

Yan Cheng Guo*, Tian Sheuan Chang, Chih Sheng Lin, Bo Cheng Chiou, Chih Ming Lai, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh Chang

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading weight or feature maps from DRAM for large AI models. Moreover, previous SRAM-based CIM architectures lack end-to-end model inference. To address these issues, this paper proposes CIMR-V, an end-to-end CIM accelerator with RISC-V that incorporates CIM layer fusion, convolution/max pooling pipeline, and weight fusion, resulting in an 85.14% reduction in latency for the keyword spotting model. Furthermore, the proposed CIM-type instructions facilitate end-to-end AI model inference and full stack flow, effectively synergizing the high energy efficiency of CIM and the high programmability of RISC-V. Implemented using TSMC 28nm technology, the proposed design achieves an energy efficiency of 3707.84 TOPS/W and 26.21 TOPS at 50 MHz.

原文English
主出版物標題ISCAS 2024 - IEEE International Symposium on Circuits and Systems
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9798350330991
DOIs
出版狀態Published - 2024
事件2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, 新加坡
持續時間: 19 5月 202422 5月 2024

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

Conference2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
國家/地區新加坡
城市Singapore
期間19/05/2422/05/24

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