@inproceedings{b7e281df41234615b57daee3bc2428e3,
title = "Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration",
abstract = "This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning techniques, the developed placer can find the solution fast with the optimized total wirelength (TWL) on half-perimeter wirelength (HPWL). Additionally, with the post placement procedure, the placer reduces maximum temperatures with slight increase of wirelength. Experimental results show that the placer can not only find better optimized TWL (reducing 1.035% HPWL) but also speed up at most two orders of magnitude than the prior art. With thermal consideration, the placer can reduce the maximum temperature up to 8.214 °C with an average 5.376% increase of TWL.",
keywords = "2.5D IC, chiplet placement, sequence pair, thermal",
author = "Chiou, {Hong Wen} and Jiang, {Jia Hao} and Chang, {Yu Teng} and Lee, {Yu Min} and Pan, {Chi Wen}",
note = "Publisher Copyright: {\textcopyright} 2023 Copyright held by the owner/author(s).; 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023 ; Conference date: 16-01-2023 Through 19-01-2023",
year = "2023",
month = jan,
day = "16",
doi = "10.1145/3566097.3567911",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "7--12",
booktitle = "ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings",
address = "United States",
}