To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.
|頁（從 - 到）||167-170|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1 12月 1994|
|事件||Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England|
持續時間: 30 5月 1994 → 2 6月 1994