Chip design of A 32-b logarithmic number system

Sheng-Chieh Huang; Liang Gee Chen; Thou Ho Chen

doi:10.1109/ISCAS.1994.409224

Chip design of A 32-b logarithmic number system

Sheng-Chieh Huang^*, Liang Gee Chen, Thou Ho Chen

^*此作品的通信作者

電機工程學系

研究成果: Conference article › 同行評審

8 引文斯高帕斯（Scopus）

摘要

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log₂(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2^0.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

原文	English
頁（從 - 到）	167-170
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	4
DOIs	https://doi.org/10.1109/ISCAS.1994.409224
出版狀態	Published - 1 12月 1994
事件	Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England 持續時間: 30 5月 1994 → 2 6月 1994

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10.1109/ISCAS.1994.409224

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引用此

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title = "Chip design of A 32-b logarithmic number system",

abstract = "To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.",

author = "Sheng-Chieh Huang and Chen, {Liang Gee} and Chen, {Thou Ho}",

year = "1994",

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doi = "10.1109/ISCAS.1994.409224",

language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) ; Conference date: 30-05-1994 Through 02-06-1994",

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T1 - Chip design of A 32-b logarithmic number system

AU - Huang, Sheng-Chieh

AU - Chen, Liang Gee

AU - Chen, Thou Ho

PY - 1994/12/1

Y1 - 1994/12/1

N2 - To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

AB - To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.

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U2 - 10.1109/ISCAS.1994.409224

DO - 10.1109/ISCAS.1994.409224

M3 - Conference article

AN - SCOPUS:0028564085

SN - 0271-4310

VL - 4

SP - 167

EP - 170

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)

Y2 - 30 May 1994 through 2 June 1994

ER -

Chip design of A 32-b logarithmic number system

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