Characterization of spatial CD variability, spatial mask-level correction, and improvement of circuit performance

Statistical characterization of gate CD variability of a production CMOS process reveals a large spatial intra-field component, strongly dependent on the local layout patterns. We present a novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design. A rigorous analysis of the impact of intra-field variability on circuit performance is undertaken. We show that intra-field CD variation has a significant detrimental effect on the overall circuit performance by reducing the average speed by up to 20%. We derive a model quantitatively relating intra-field CD variance to circuit delay degradation. We propose a mask-level spatial gate CD correction algorithm to reduce the intra-field and overall variability, resulting in circuit performance improvement, and provide an analytical model to evaluate the effectiveness of correction for variance reduction.